Indistinguishable From Magic: Manufacturing Modern Computer Chips

There's a brilliant talk, given in 2009 at HOPE09, NYC titled "Indistinguishable From Magic: Manufacturing Modern Computer Chips". At roughly 36 minutes, there's a cross-section of a (in 2009) modern chip. The topmost layer is the shiny rainbowy topmost metal-layer you see on typical (from the top) die photographs. The very, very small comb-looking bottommost-layer is the individual transistors, and structures there are of the size that give a "xxx nm" process its name. [this video] I very much recommend everyone to watch this video, to get a sense for the complexity that goes into producing a modern CPU. To come back to the thread I'm answering here: The logic analyzer on the Alto (probing microcode) connected to interconnects of individual gates probably would be connected to signals somewhere in the lower middle of the stack in a modern CPU, I guess.

It takes years just to figure out how to use the machines to produce actual working chips. They're the most specialized, intricate, expensive machines in the world. They're operated in enormous clean rooms that only allow for 1 half-micron sized particle per cubic foot. No fab is going to run them without exactly following the procedures they have spent billions developing and testing. They are also going to avoid potential delays as much as possible because these machines have to be running for as much of their useful life as possible to recoup the vast expense. The level of risk-averseness is insane, but warranted. If you haven't watched this video, I highly recommend it: Indistinguishable From Magic: Manufacturing Modern Computer Chips [this video] It's a little outdated now, but very comprehensive and gives you an idea of how totally nuts the chip business is.

I do not have the answers for your questions (and I don't think anyone can share actual failure rates), but I would direct you this video which goes over a lot of modern chip fabrication techniques, circa 2009: [this video] It's crazy stuff. There are wafer test machines which will interface with the wafer directly and do some testing (which are $$$$), JTAG type tests, which access parts of the chip out of band, and functional testing. Some products, like SD Cards actually have a microcontroller on board that will provide the test routines and error correction without the need of an expensive machine. Design for test is extremely important. I'm by no means an expert however, I mostly deal with JTAG and functional tests.

Just doing some napkin math to give myself some other context in my own head with something much smaller, die size for the Apple A14 isn't out yet, but the A13 (found in the iPhone 11 series and SE 2) is around 98mm^2 manufactured on TSMC's 2nd gen 7nm N7P. A14 might be something like that, because while it's a smaller process Apple boosted transistor count by 38% as well. Lazily/conservatively taking off 10mm on the edge for squares into a circle, that'd be about 630 chips per N5 wafer, a high enough count that chip loss rate shouldn't be too far from defect rate. Even assuming they can get 90% yield right out the gate (maybe generous) that's still about $30/chip, just for manufacturing without any R&D amortization, packaging etc. That actually seems not insignificant going by historical iPhone BOMs [1], so even for smartphones with their far far smaller SoCs 5nm at launch isn't nothing. The continued ongoing progress in silicon is just mindblowing when you dig into the details in any real way. I was blown away already watching the "Indistinguishable From Magic: Manufacturing Modern Computer Chips" [2] presentation years ago, which still seems incredible and yet that's all talking about now ancient tech. The increasing costs and design challenges though are also going to have interesting effects on the industry, as who/what has the margins to afford fabbing aggressive chips on the cutting edge might start to diverge a bit more. I also wonder how longevity will be, I remember

This is strikingly similar to the process used in modern offset printing. As a young child, I grew up in a family printing business, and though I didn't learn all the details (I didn't really have much interest in the printing side of the business and spent most of my time in the then still very early digital prepress playing with the computers). My earliest memories of it were marked by specialists doing digital typography on specialist computers, one monitor was a green-screen where some kind of markup was entered and the other screen was a raster monitor where the output was rendered. Each block of text was "printed" on photographic paper, cut and then sent to the "layout" department where it was taped or wax adhered to a page. (If this is hard to picture, imagine taping each block of text from this page [1] onto another piece of paper in order to layout the entire page.) The process looked a bit like this [2] Then the final page was photographed in a photography room and the negative developed. On occasion a photographic "proof" would be developed to show the final page layout and make sure there weren't any artifacts from all these tiny little pieces of paper that were used to make up the text blocks. Then the negative was used as a lithographic mask to "burn" the image of the page onto a metal sheet which then went through some kind of chemical bath to etch the image onto the sheet. From that point the process was basically what's in the rest of this video [3]. And one