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RAAIS 2017 - Simon Knowles, Co-Founder and CTO of Graphcore

Name: RAAIS 2017 - Simon Knowles, Co-Founder and CTO of Graphcore
Description: Simon Knowles, co-founder and CTO of Graphcore, talks about "intelligence processors", chips designed specifically for machine learning. The talk was given at the RAAIS 2017 summit and covers Graphcore's architecture.

The Research and Applied AI Summit - RAAIS Talks advanced partly dated

Open on YouTube First HN thread

3 HN users recommended this talk in 3 different months between 2017 and 2018.

2007–2026

3 recommendations HackerTube score 3

HN points to it as a technical talk from a chip designer on why AI hardware should put memory close to compute and use async data transfers.

Simon Knowles, co-founder and CTO of Graphcore, talks about "intelligence processors", chips designed specifically for machine learning. The talk was given at the RAAIS 2017 summit and covers Graphcore's architecture.

Pull quote: “Here's a nice technical talk from Graphcore's CTO about that” (HN, 2017)

Also tagged: ai accelerator chips, graphcore, ai hardware, deep learning, processor architecture, memory bandwidth

What Hacker News said

3 labeled comments from the HN archive; up to 20 are kept per video, favoring different commenters. Each one links back to the original thread.

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Graphcore's approach of memory near compute and async transfers.

Interesting approach, but very far off. I prefer GraphCore as a promising new lead in AI hardware. Moving computation close in with memory, and making data transfers async will speed up DL. [this video]

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Recommends midko November 2017 under Intel to Develop Discrete GPUs, Hires AMD's Raja Koduri as Chief Architect

Technical talk from Graphcore's CTO on new AI chips.

Indeed, and that's why there are a couple of startups working on new chips and why Google has the TPU. Here's a nice technical talk from Graphcore's CTO about that [this video]

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Recommends maffydub April 2018 under The Looming Battle Over AI Chips

Overlaps heavily with a talk on Graphcore's tile architecture and power.

Read the full comment

I went to a talk from the CTO of Graphcore ( [link] ) on Monday. They are designing chips targeted at machine learning. As I understood it, their architecture comprises - lots of "tiles" - small processing cores with collocated memory (essentially DSPs) - very high bandwidth (90TB/s!) switching fabric to move data between tiles - "Bulk Synchronous Parallel" operation, meaning that the tiles do their work and then the switching fabric moves the data, and then we repeat. The key challenge he pointed to was power - both in terms of getting energy in (modern CPUs/GPUs take similar current to your car starter motor!) and also getting the heat out. Logic gates take a lot more power than RAM, so he argued that collocating small chunks of RAM right next to your processing core was much better from a power perspective (meaning you could then pack yet more into your chip) as well as obviously being better from a performance perspective. [this video] isn't quite the presentation I saw, but it has quite a lot of overlap. Hope that helps!

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